Altera zeros out power with new MAX® IIZ CPLDs

Expanding its low-power portfolio of programmable logic solutions, Altera Corporation announced the new, zeropower MAX® IIZ CPLD designed specifically to address the power, package and price constraints of the portable applications market.

Offering a resource advantage of up to six times the density and three times the I/Os compared to competing traditional macrocell- based CPLDs, MAX® IIZ devices allow designers to meet changing functional requirements at the same or lower power while saving board space. Adding zeropower and ultra-small packages to the most popular CPLD series in the industry, the MAX® IIZ devices deliver the many benefits of CPLDs – including flexibility, faster time to market, and board-level integration – to handsets and other portable applications.

Features and Benefits of MAX® IIZ CPLDs

MAX® IIZ devices are available in densities of 240 and 570 logic elements (LEs). The devices are available in ultrasmall MBGA packages with up to 160 I/Os. This increased logic density and greater I/O count allow greater integration of existing functions from other devices, substantially reducing board space and power consumption while lowering overall system costs.

MAX® IIZ devices break through the power, space and cost limitations of traditional macrocell- based CPLDs by combining non-volatility and instant-on performance with an innovative look-up table (LUT) logic structure. The devices utilize a 0.18-micron process, 1.8V core voltage and 6-metal-layer flash to provide both high functionality and zero-power consumption in a single device. The advanced system features of MAX® IIZ CPLDs, such as user flash memory, an internal oscillator, cost optimization, greater density, smaller packages and lower power consumption, far surpass those of all traditional macrocell-based CPLDs.

Balance Requirements for Low Power Consumption, small Packages and Low Cost with MAX® IIZ CPLDs

>	Low power consumption – as low as 29 μA, for the industry’s lowest static and dynamic power consumption. MAX® IIZ CPLDs meet the needs of the most demanding low-power applications by offloading common system tasks from power-hungry ASSPs.

>	Ultra-small packages – as small as 5 x 5 mm. MAX® IIZ CPLDs provide up to 6X the density and 3X the I/O resources in the same package sizes as traditional macrocell-based CPLDs. This means you can pack greater functionality into a smaller PCB space.

>	Greater logic integration at a lower price. Cost-effective MAX® IIZ CPLDs will help you deliver feature rich portable products at competitive prices.

>	Greater density and I/O allows MAX® IIZ CPLDs to operate as low-power coprocessors that offload system tasks from big power-hungry host processors.

For more information on MAX® IIZ devices, visit www.altera.com/b/maxiiz.html.
For more information on MAX® IIZ devices in portable applications, visit www.altera.com/b/maxiiz-portable.html.

Power Consumption Measurement Design Examples

There is a power consumption measurement design example included with the demonstration board CD-ROM. The board and design example allow you to take power measurements of the CPLD when operating in four modes of system operation. Table 1 describes the system and CPLD conditions for these common system modes. The functional design implemented is a “clock,” displaying the time of day.

Design engineers typically define high speed as a system clock running at 20 MHz or faster. MAX® IIZ CPLDs have more than 50 percent lower dynamic power versus competing CPLDs. Dynamic power is dependent on the system clock, so using MAX® IIZ CPLDs result in the lowest power for high-speed applications. Low speed is defined as less than 10MHz, but is typically in the kHz range.

One of the best techniques for lowering system power consumption is to selectively turn off components when they are not being used. MAX® IIZ devices are the only CPLDs with an internal oscillator, allowing the device to automatically power off. For more information, see AN 491: Auto Start Using MAX® II CPLDs design example (PDF).

Another related theme is using a CPLD as a low-power coprocessor. This webcast shows how adding a CPLD to your design can actually lower total system power 50x to 100x by offloading simple system tasks from a powerhungry embedded processor or ASSP to a power-frugal MAX® IIX CPLD.

There are four power measurement options on the MAX® IIZ CPLD demonstration board. You can probe the following power rails with a portable multi-meter:
> MAX® IIZ CPLD, core only
> MAX® IIZ CPLD, I/O bank 1
> MAX® IIZ CPLD, I/O bank 2
> Entire demonstration board

Software Support

MAX® IIZ devices are supported by free Quartus® II Web Edition software version 7.2, SP1. With this new version of the easy-to-use Quartus II software, Altera delivers the lowest development cost and fastest time to design completion to ensure a smooth and successful design flow. The Quartus II software also integrates seamlessly with all leading third-party synthesis and simulation tools. Customers can download the subscription edition and web edition of the Quartus II software at www.altera.com/download

Pricing and Availability

Production-qualified MAX® IIZ EPM240Z M68 devices will begin shipping in the first quarter of 2008 at US$1.25 in high volumes.
All MAX® IIZ devices will be shipping in production by the second quarter of 2008.
Additionally, over 20 MAX® IIZ design examples, enabling designers to quickly and cost effectively create and customize their designs, are available at www.altera.com/max2example

The MAX® IIZ demo board will be available by the second quarter of 2008.

For detailed specifications please contact your local Sasco Holz Branch Office.