LPRP – The reference Platform for low Power FPGA Designs and Handheld Applications

The market demand for complex but power sensitive embedded systems is growing constantly.

It has not been previously feasible to consider FPGA’s that can be powered by portable battery sources. However reductions in device geometries have significantly reduced static and dynamic power requirements for these devices.
Arrow Electronics in cooperation with Altera and Linear Technology has developed a low-power reference platform (LPRP) using latest FPGA families and power management functions as well as software design techniques for maximum power savings to deliver a portable platform capable of evaluating FPGA based handheld applications.

The LPRP features Altera’s latest Cyclone® III FPGA family and Linear Technology’s newest power management devices to achieve maximum power savings while improving overall system performance.

PMF (Power Management Framework)

The LPRP demonstrates board, chip level, low power and power management design techniques that allow portable, battery operated products to be based on Altera Cyclone® III FPGAs.
The LPRP features a Board Level Power Management Framework (PMF). This framework uses techniques to conserve power in the Cyclone® III FPGA and board level. The PMF is a layer of software run on the Nios II processor in the Cyclone® III FPGA and on an additional micro controller. Five different board Power modes have been defined.

The modes are normal, reduced, standby, hibernate and power-off LPRP Kit includes:

> LPRP development board (functions as MP3 player and picture viewer)
> Detailed LPRP User Guide and reference materials on SD card with reader
> Quick Start guide
> Pair of headphones
> USB cable

The LPRP can be used to demonstrate low power designs provided with the kit or to develop new ones.
It features the devices listed below:

> EP3C25 Cyclone® III low cost/low power FPGA
> Power converters form Linear Technology including the LTC3455
> CellularRAM, NOR FLASH and removable SD FLASH memory devices
> 1.1 Inch monochrome grayscale display
> Audio CODEC and headphone amplifier
> Analog to digital converters
> Buttons & LEDS
> General purpose I/O header
> Ultra low power microcontroller

The LPRP has built in JTAG debug hardware that can be used to:

> Download hardware images to the Cyclone® III FPGA
> JTAG debug the Nios II processor embedded in the FPGA
> Communicate with the JTAG UART embedded in the FPGA
> Communicate with the SignalTap II Logic Analyzer embedded in the FPGA

Design Examples included

Arrow-developed intelligent board-level power management IP technology, low power cellular RAM interfacing, USB or Li-Ion battery powered operation and multiple power saving system modes are available for immediate evaluation.

Included design examples:

> MP3 player
> Photo viewer

For more information about Altera Cyclone® III EP3C25:
For more Cyclone® III information, please go to: www.altera.com/cyclone3
For detailed device specifications, please see the Cyclone® III datasheet: www.altera.com/literature/lit-cyc3.jsp

For more information about Linear Technology LT3455, please go to www.linear.com and select LT3455 in the search function.
To download SwitcherCAD software please go to: www.linear.com/designtools/software/switchercad.jsp